CRCERR=CRCERR_0, TWRNINT=TWRNINT_0, TXWRN=TXWRN_0, WAKINT=WAKINT_0, TX=TX_0, FRMERR=FRMERR_0, ACKERR=ACKERR_0, RXWRN=RXWRN_0, BIT1ERR=BIT1ERR_0, BOFFINT=BOFFINT_0, RWRNINT=RWRNINT_0, ERRINT=ERRINT_0, RX=RX_0, BIT0ERR=BIT0ERR_0, SYNCH=SYNCH_0, STFERR=STFERR_0, FLTCONF=FLTCONF_0, IDLE=IDLE_0
Error and Status 1 Register
| WAKINT | When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm 0 (WAKINT_0): No such occurrence 1 (WAKINT_1): Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode |
| ERRINT | This bit indicates that at least one of the Error Bits (bits 15-10) is set 0 (ERRINT_0): No such occurrence 1 (ERRINT_1): Indicates setting of any Error Bit in the Error and Status Register |
| BOFFINT | This bit is set when FLEXCAN enters ‘Bus Off’ state 0 (BOFFINT_0): No such occurrence 1 (BOFFINT_1): FLEXCAN module entered ‘Bus Off’ state |
| RX | This bit indicates if FlexCAN is receiving a message. Refer to . 0 (RX_0): FLEXCAN is receiving a message 1 (RX_1): FLEXCAN is transmitting a message |
| FLTCONF | If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate “Error Passive” 0 (FLTCONF_0): Error Active 1 (FLTCONF_1): Error Passive 2 (FLTCONF_2): Bus off |
| TX | This bit indicates if FLEXCAN is transmitting a message.Refer to . 0 (TX_0): FLEXCAN is receiving a message 1 (TX_1): FLEXCAN is transmitting a message |
| IDLE | This bit indicates when CAN bus is in IDLE state.Refer to . 0 (IDLE_0): No such occurrence 1 (IDLE_1): CAN bus is now IDLE |
| RXWRN | This bit indicates when repetitive errors are occurring during message reception. 0 (RXWRN_0): No such occurrence 1 (RXWRN_1): Rx_Err_Counter >= 96 |
| TXWRN | This bit indicates when repetitive errors are occurring during message transmission. 0 (TXWRN_0): No such occurrence 1 (TXWRN_1): TX_Err_Counter >= 96 |
| STFERR | This bit indicates that a Stuffing Error has been detected. 0 (STFERR_0): No such occurrence. 1 (STFERR_1): A Stuffing Error occurred since last read of this register. |
| FRMERR | This bit indicates that a Form Error has been detected by the receiver node, i 0 (FRMERR_0): No such occurrence 1 (FRMERR_1): A Form Error occurred since last read of this register |
| CRCERR | This bit indicates that a CRC Error has been detected by the receiver node, i 0 (CRCERR_0): No such occurrence 1 (CRCERR_1): A CRC error occurred since last read of this register. |
| ACKERR | This bit indicates that an Acknowledge Error has been detected by the transmitter node, i 0 (ACKERR_0): No such occurrence 1 (ACKERR_1): An ACK error occurred since last read of this register |
| BIT0ERR | This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message 0 (BIT0ERR_0): No such occurrence 1 (BIT0ERR_1): At least one bit sent as dominant is received as recessive |
| BIT1ERR | This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message 0 (BIT1ERR_0): No such occurrence 1 (BIT1ERR_1): At least one bit sent as recessive is received as dominant |
| RWRNINT | If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from ‘0’ to ‘1’, meaning that the Rx error counters reached 96 0 (RWRNINT_0): No such occurrence 1 (RWRNINT_1): The Rx error counter transition from < 96 to >= 96 |
| TWRNINT | If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from ‘0’ to ‘1’, meaning that the Tx error counter reached 96 0 (TWRNINT_0): No such occurrence 1 (TWRNINT_1): The Tx error counter transition from < 96 to >= 96 |
| SYNCH | This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process 0 (SYNCH_0): FlexCAN is not synchronized to the CAN bus 1 (SYNCH_1): FlexCAN is synchronized to the CAN bus |